----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:01:35 03/25/2011 
-- Design Name: 
-- Module Name:    port - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.definitions.ALL;
use std.textio.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity puerto is
	 Port ( acc : in port_addr_type;
			  is_in : in STD_LOGIC;
			  is_out : in STD_LOGIC;
			  proc_state : in processor_state;
           port_cyc_o : out  STD_LOGIC;
           por_stb_o : out  STD_LOGIC;
           port_we_o : out  STD_LOGIC;
           port_ack_i : in  STD_LOGIC;
           port_addr_o : out  port_addr_type;
			  
end puerto;

architecture Behavioral of puerto is

begin
process (proc_state, is_in, is_out)
	begin
	if ((proc_state=execute) then
		if (is_in='1' or is_out='1') then			
			port_stb_o <= '1';
			port_cyc_o <= '1';
			if (is_out='1') then
				port_we_o='1';
			end if;
			if (is_in='1') then
				port_we_o='1';
			end if;
			port_addr_o <= acc;
		end if;
	if ( (proc_state=execute and port_ack_i='1') or (proc_state=mem and port_ack_i='1')) then
		port_cyc_o <= '0';
		port_stb_o <= '0';
	end if;
	end process;

end Behavioral;

